It is common in the art to combine bipolar transistors and complementary metal-oxide silicon ("CMOS") field effect transistors in a bipolar-complementary metal-oxide-silicon ("BiCMOS") transistor configuration. BiCMOS configurations are widely used in fabricating ever smaller, faster and increasingly complex integrated circuits. BiCMOS integrated circuits are fabricated layer-by-layer, typically on a silicon substrate, with one or more layers at least partially covered with an oxide such as SiO.sub.2.
In general, high cut-off frequency performance is desired in a BiCMOS circuit. Such high frequency performance is enhanced by providing small geometry bipolar devices with reduced emitter-base junction area and junction capacitance. Smaller geometry devices not only promotes operating speed, but also allows greater device density within a BiCMOS circuit. However in BiCMOS fabrication, process steps that create small geometry bipolar devices frequently cannot be used to simultaneously create MOS devices. The inability to make dual use of many processing steps thus adds to the complexity of BiCMOS fabrication, and can result in reduced device yield.
Another undesired effect of scaling down device size is degraded device performance, especially junction leakage and degradation of current gain. Scaling down device dimensions and increasing doping concentrations tends to increase electric field intensities to which the devices are exposed, since operating potentials are generally fixed. For example, reverse biased depletion regions within a small geometry bipolar transistor can be subjected to relatively high intensity electric fields.
Electrons encountering these increased field intensities acquire increased kinetic energy and accelerate beyond an equilibrium state, becoming what is commonly termed "hot electrons" or "hot carriers". Hot carriers can escape from the semiconductor, surmount and remain trapped within an oxide layer within the device.
More specifically, the trapped charges form a local depletion region, wherein holes and electrons recombine, typically with a decreased surface recombination lifetime. Unfortunately the holes required to neutralize or satisfy the surface recombination current are holes diverted from the transistor's base current. The resultant surface effect decreases the transistor current gain (.beta.). The result is degraded bipolar performance.
It is known in the art that providing a sharp emitter-base transition will result in high current gain (.beta.). However forming such emitter-base regions in small geometry devices using BiCMOS compatible techniques is challenging because of the difficulty in independently controlling the junction depths of the variously doped regions.
It is known in the art to improve high frequency performance by reducing the extrinsic base resistance of a bipolar transistor by increasing base junction dopant levels. Unfortunately, under reverse bias conditions, increased dopant concentrations result in smaller depletion regions, which increases the electric field to which the emitter-base junction is subjected. This in turn can produce increased numbers of hot carriers, with resultant degradation of device performance.
It is known in the art to suppress hot carrier effects using a laterally graded emitter structure that decreases peak electric fields between the emitter and base regions of a transistor. See for example H. Honda, et al., I.E.E.E. CH2865-4/90/0000-0227 (1990). Although it is recognized in the art that a sharp emitter-base transition improves bipolar current gain .beta., the method disclosed by Honda, et al. does not readily allow independent control over the bipolar transistor's base width and active region, or the profile of the laterally graded emitter for purposes of optimizing bipolar performance.
In short, while contemporary integrated circuit design demands smaller device size, smaller device size is accompanied by significant hot carrier effects that degrade bipolar transistor performance. What is needed is a manufacturing process permitting optimization of junction device parameters to produce a laterally graded emitter that decreases hot carrier generation in a bipolar device. The emitter-base junction in such a device should have a sharp transition, further promoting high current gain. Preferably such process should be BiCMOS compatible, allowing bipolar and CMOS fabrication steps to occur simultaneously on a common integrated circuit substrate. The present invention discloses such a process.